Each Subslice contains 6 or 8 (or 10 in Haswell GPUs) EUs and a sampler, and has 64 KB shared memory.Only one of the FPUs supports 32-bit integer instructions. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. One supports FP32 and FP64, and the other supports only FP32. Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation.Main article: Intel Graphics Technology § Gen7 Specifications of Intel HD Graphics series Graphics The entire GPU shares a sampler and an ROP.Double peak performance per clock cycle compared to previous generation due to fused multiply-add instruction.Main article: Intel Graphics Technology § Gen6 Specifications of Intel Gen5 graphics processing units Name Hierarchical-Z compression and fast Z clear.Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle.Integrated graphics chip moved from motherboard into the processor.Main article: Intel Graphics Technology § Gen5 Each EU has a 128-bit wide FPU that natively executes four 32-bit operations per clock cycle.Full hardware DirectX 10 support starting with GMA X3500. The last generation of motherboard integrated graphics. Variable-Length Decoding (VLD) + iDCT + MC (Full) Intel's first DirectX 9 GPUs with hardware Pixel Shader 2.0 support. These chips added support for texture combiners allowing support for OpenGL 1.3. Intel marketed its second generation using the brand Extreme Graphics.
Optional external MPEG-2 decoder via Video Module Interface
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